NEW REQUIREMENTS

SEMICONDUCTOR : Analog Layout Design Engineer

Work Location : Bangalore / Beijing / Hubli / Moscow / Singapore

Work Expertise : 4 - 8 years

Job Specs :

Expertise in Analog Layout design
Expertise in planner technology node / higher node 180 nm is mandatory
Expertise in EMIR analysis, ESD, antenna and related layout solutions
Knowledge of advanced technology nodes (7nm & below)
Good understanding of advanced semiconductor technology process and device physics.
Full-custom circuit layout/verification and RC extraction experience
Familiar with Cadence Virtuoso environment and various industry physical verification tools (DRC,LVS,DFM etc)
Preferred resources with valid regional work permit

SEMICONDUCTOR : DFT Engineer

Work Location : Bangalore / Beijing / Ireland / Malaysia / Moscow

Work Expertise : 6 - 12 years

Job Specs :

Architect, Implement, and validate innovative DFT techniques on test-chips and hard-macros
Insert DFT logic into SoC-style designs at the RTL level and at the Synthesis gate level, validate all features, and generate ATE-targeted test patterns to be run on silicon
Work closely with front-end design and verification teams on DFT RTL level insertion, back-end synthesis, place-and-route, and static-timing-analysis teams on DFT gate level insertion and timing closure, and Test and Debug teams on silicon characterization and validation
Expertise in scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debug
Expertise with Siemens, Cadence and/or Synopsys DFT and simulation tools
Preferred resources with valid regional work permit

SEMICONDUCTOR : Memory Layout Design Engineer

Work Location : Bangalore / Beijing / Moscow / Singapore

Work Expertise : 4 - 8 years

Job Specs :

Expertise in working on memory layout design for advanced nodes ( TSMC 3nm, 5nm,), including FinFET architecture and challenges such as variability and manufacturability
Expertise in working on address process-dependent effects like electro-migration (EM), IR drop Expertise in optimizing layouts for yield enhancement and manufacturing robustness
Expertise in performing debugging of silicon failures and identify layout-related issues
Create detailed and optimized physical layouts for memory cells, arrays, and peripheral circuits using tools like Cadence Virtuoso or Synopsys Custom Compiler
Perform parasitic extraction and ensure compliance with DRC (Design Rule Check) and LVS (Layout Versus Schematic) rules
Work closely with circuit designers to ensure the layout meets electrical and performance specifications, such as timing, power, and area (PPA)
Provide feedback on circuit designs to improve layout efficiency
Utilize EDA tools for layout design, simulation, and verification, ensuring compliance with foundry-specific PDKs (Process Design Kits)
Automate repetitive tasks and improve workflow efficiency using scripting (e.g., Python, SKILL)
Preferred resources with valid regional work permit

SEMICONDUCTOR : Synthesis & Timing Engineer (STA)

Work Location : Bangalore / Beijing / Moscow / Singapore

Work Expertise : 4 - 8 years

Job Specs :

Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design.
Set up and configure STA tools (e.g., Cadence Encounter, Synopsys PrimeTime) for the analysis, including library characterization, delay models, and clock definitions.
Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics. Ensure that the design meets timing requirements for various corners and operating conditions (e.g., process, voltage, temperature variations).
Identify and analyze asynchronous signals crossing between different clock domains to ensure proper synchronization and to avoid metastability issues.
Define and analyze multicycle paths and false paths to accurately capture the designs timing constraints.
Collaborate with RTL and physical design teams to achieve timing closure by optimizing the design or constraints. Perform incremental and formal ECO (Engineering Change Order) analysis to address timing issues.
Work with CTS / clock tree synthesis engineers to ensure that the clock tree meets timing requirements and minimizes clock skew and jitter.
Perform post-layout STA to account for parasitic capacitance and resistance effects introduced during the physical design phase. Identify and resolve timing violations and sign-off on the final timing closure.
Analyze timing margins to account for variability and manufacturing process variations, ensuring robust operation.
Prepare detailed timing analysis reports, including timing paths, violations, and suggestions for timing optimization.
Collaborate closely with RTL designers, physical designers, DFT (Design for Test) engineers, and verification teams to resolve timing-related issues.
Contribute to the development and improvement of STA methodologies and flows to enhance efficiency and accuracy.
Preferred resources with valid regional work permit