SEMICONDUCTOR : ASIC DFT ENGINEER

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Work Location  : Bangalore, Hyderabad, Pune, Remote

Work Expertise : 5 - 13 years

Job Specs         :      

• B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering.   
• Expertise in Design for Test / DFT
• Expertise in Scan compression and insertion
• Expertise in Memory BIST / Logic BIST,
• Expertise in JTAG / IJTAG
• Expertise in ATPG
• Expertise in fault simulation, back-annotated gate-level verification, silicon debug
• Expertise in coding using Verilog RTL, 
• Expertise in Perl / TCL scripting
• Proficient in Unix / Linux environments
• Expertise with Siemens, Cadence, and/or Synopsys DFT and simulation tools
• Resources opting for remote working option should have 8 Years - 10 years of relevant technical expertise including 2 + years of remote working expertise
• Resources opting for remote working option should be citizens of India and residing in any state or union territories of India 

Work Location  : Bangalore, Hyderabad, Singapore Remote

Work Expertise : 6 - 13 years

Job Specs         :      

• B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering.   
• Expertise in ASIC / Digital physical design
• Expertise in Cadence tools: Innovus, Tempus, QRC, Voltus, Genus, Conformal LEC
• Expertise in Synopsys tools: ICC2, ICV, PrimeTime, DC, Formality, PTPX
• Expertise in Physical Verification using Mentor Calibre or Cadence PVS
• Expertise in Low-Power Design and UPF methodology
• Expertise in scripting using TCL / Shell / Perl / Python
• Good knowledge of IT infrastructure and LSF
• Resources opting for remote working option should have 8 Years - 10 years of relevant technical expertise including 2 + years of remote working expertise
• Resources opting for remote working option should be citizens of India and residing in any state or union territories of India 

Work Location  : Bangalore, Hyderabad, Remote 

Work Expertise : 6 - 10 years

Job Specs         :      

• B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering. 
• Expertise in the definition of architecture and microarchitecture features for the block
• Expertise in developing the logic design
• Expertise in working on DDR memory controllers 
• Expertise in CDC / RDC
• Expertise in Lint
• Expertise in register transfer level (RTL) coding
• Expertise in simulation of SoC design and integration of IP blocks and subsystems into a full chip SoC or discrete component design. 
• Expertise in performing quality checks for various logic design aspects ranging from RTL to timing/power convergence. 
• Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation. 
• Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. 
• Follows secure development practices to address the security threat model and security objects within the design. 
• Works with IP providers to integrate and validate IPs at the SoC level. 
• Drives quality assurance compliance for smooth IP SoC handoff. 
• Resources opting for remote working option should have 8 Years - 10 years of relevant technical expertise including 2 + years of remote working expertise
• Resources opting for remote working option should be citizens of India and residing in any state or union territories of India 

Work Location  : Bangalore

Work Expertise : 10 - 18 years

Desired Profile  :        

• Bachelor's / Master's degree in engineering from EEE / E&C with expertise in mixed-signal or CMOS circuit design
• Expertise in analog blocks like power management DC-DC convertor, LDOs 
• Expertise in designing ADC / DAC/ PLLs or Experience in simulation or characterization of IO cells
• Design and architect CMOS analog and mixed-signal integrated circuits
• Simulate designs with state-of-the-art CAD tools
• Document designs and simulation results 
• Expertise with high-speed SERDES circuits
• Knowledge of layout issues
• Expertise with circuit simulators (HSPICE, Spectre, etc)
• Expertise with Cadence Design Environment is an asset
• Expertise in PERL and UNIX shell scripting languages
• Expertise in managing and leading mixed signal design  teams across different continents 
• Expertise in leading business strategy in the VLSI / Semiconductor Services / foundry business industry 
• Expertise in managing end to end projects including tape outs
• Must be willing to travel at short notice, relocate as per business needs 
• Must be willing to work onsite (customer premises) as per business needs

Job Specs  : 

• Responsible for meeting delivery, revenue, operational, customer satisfaction targets and team management
• Hire and manage high caliber technical teams across GCC, ODC and onsite
• Develop, Drive high quality business / technology strategy and oversee the translation of this strategy into tactical action
• Uphold the organization's culture and long term missions
• Liaise and negotiate with various partners around the world to bring in new partnership.
• Synergize all company's resources and talents for the growth of company's business
• Oversee all sectors and fields of the business to ensure the company's competitiveness
• Provide leadership, direction, major decision making and resolution support to operations, projects and staff.
• Build strategic business partnerships and execute these opportunities through collaboration with external partners 

Work Location  : Bangalore, Malaysia

Work Expertise : 10 - 18 years 

Desired Profile  :

• Expertise in Design for Test / DFT
• Expertise in coding using Verilog RTL, and scripting language like TCL, and/or Perl
• Proficient in Unix/Linux environments
• Expertise in Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debug
• Expertise with Siemens, Cadence, and/or Synopsys DFT and simulation tools
• Expertise in managing and leading DFT technical teams across different continents 
• Expertise in leading business strategy in the VLSI / Semiconductor Services / foundry business industry 
• Expertise in managing end to end projects including tape outs
• Must be willing to travel at short notice, relocate as per business needs 
• Must be willing to work onsite (customer premises) as per business needs
• VISA / WORK PERMIT SPONSORED

Job Specs  : 

• Responsible for meeting delivery, revenue, operational, customer satisfaction targets and team management
• Hire and manage high caliber technical teams across GCC, ODC and onsite
• Develop, Drive high quality business / technology strategy and oversee the translation of this strategy into tactical action
• Uphold the organization's culture and long term missions
• Liaise and negotiate with various partners around the world to bring in new partnership.
• Synergize all company's resources and talents for the growth of company's business
• Oversee all sectors and fields of the business to ensure the company's competitiveness
• Provide leadership, direction, major decision making and resolution support to operations, projects and staff.
• Build strategic business partnerships and execute these opportunities through collaboration with external partners 

Work Location  : Bangalore, Beijing, Hyderabad, Pune, Taiwan

Work Expertise : 4 - 15 years

Job Specs         :      

• Expertise in Digital Verification 
• Expertise in Functional Verification 
• Expertise in SOC / IP Verification
• Expertise in working on system Verilog assertions & test benches
• Expertise in working on OVM / UVM / VMM based verification flow
• Expertise in working on ARM processor
• Expertise in working on AMBA bus protocols  (AXI, AHB, APB) 
• Expertise in CXL or PCIe or UCIe Protocol Verification
• Expertise in simulation tools (VCS, ModelSim, Questa)
• Expertise in driving Verification Strategy, writing Test Plan, developing Test Bench, Test cases.
• Expertise in analysing Code Coverage, Functional Coverage and Assertions.
• Expertise in verification of complex SoCs.
• Expertise in Test Plan creation and Verification technologies like Code Coverage, Functional coverage, assertion based verification.
• Expertise in Verification of complex datapath, DSP based ASICs 
• 4+ years of expertise in PCIe & AXi  protocols or ethernet Protocol or DDR or sub system verification or UCIe protocol is mandatory for Bangalore requirement
• 6+ years of expertise in JTAG / AXi  protocols is mandatory for Hyderabad requirement
• 4+ years of expertise in MAC Protocol: USB, WiFi  is mandatory for Pune requirement
• Good knowledge in gate-level simulation, and Scripting languages like Python, TCL
• Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan are the preferred work locations 
• Preferred resources with valid regional work permit.

Work Location  : Bangalore, Mysore

Work Expertise : 15+ years

Desired Profile  :       

• Bachelor's / Master's degree in engineering from EEE / E&C 
• Expertise in managing and leading technical teams across different continents 
• Expertise in leading business strategy in the VLSI / Semiconductor Services / foundry business industry 
• Expertise in managing end to end projects including tape outs
• Must be willing to travel at short notice, relocate as per business needs 
• Must be willing to work onsite (customer premises) as per business needs
• Expertise in working on any of the following technologies is mandatory :

1. ANALOG MIXED SIGNAL LAYOUT - finfet / high speed / planar technology nodes
2. ANALOG DESIGN - data converter / power management / pll
3. ANALOG VERIFICATION
4. ASIC PHYSICAL DESIGN
5. ASIC RTL DESIGN 
6. DFT DESIGN - jtag / mbist / lbist / scan
7. DIGITAL VERIFICATION - OVM / UVM / VMM
8. EDA CAD FLOW - tcl / primetime / design compiler

Job Specs         :       

• Responsible for meeting delivery, revenue, operational, customer satisfaction targets and team management
• Hire and manage high caliber technical teams across GCC, ODC and onsite
• Develop, Drive high quality business / technology strategy and oversee the translation of this strategy into tactical action
• Uphold the organization's culture and long term missions
• Liaise and negotiate with various partners around the world to bring in new partnership.
• Synergize all company's resources and talents for the growth of company's business
• Oversee all sectors and fields of the business to ensure the company's competitiveness
• Provide leadership, direction, major decision making and resolution support to operations, projects and staff.
• Build strategic business partnerships and execute these opportunities through collaboration with external partners 
• Resource must be a citizen of India residing across any states / UT's of India

Work Location  : Bangalore, Israel, Moscow, Taiwan

Work Expertise : 10 - 15 years 

Desired Profile  :       

• Expertise in ASIC PD.
• Expertise in digital physical design
• Expertise in EDA synthesis, APR, STA tools and methodologies
• Expertise in one or more of the following tools ICC, ICC2, Innovus, Olympus
• Working knowledge of one or more of the following tools Primetime, Calibre, and Red hawk
• Expertise in working with multi modes and multi corners STA
• Working Knowledge of multiple power planes and multiple VT libraries
• Basic domain knowledge of EM, IR, RV analysis, Noise and Formal Equivalence Verification
• Good at scripting languages PERL, TCL, shell
• Expertise in EDA tools for the design and implementation of 100 ~ 400 million gate integrated circuits in 12nm* / 7nm* / 5nm / 3nm / 2nm process technologies
• Worked on at least 2 tape ins of moderate to high speed designs with multiple power planes
• Debug, fix, and validate pre- and post-silicon IP/sub-system logic issues and bugs
• Expertise in one or more of the following circuit design fields is an advantage: clock tree optimization, Timing analysis, and Power optimization
• Expertise in making ECOs both Metal and logic level ecos
• Expertise in DRC and LVS cleanup of designs during sign off
• Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations 
• Preferred resources with valid regional work permit

Work Location  : Bangalore, Beijing, Moscow, Noida,  Vietnam

Work Expertise : 7 - 12 years 

Job Specs         :      

• Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design.
• Set up and configure STA tools ( PrimeTime, StarRC, Tempus, Innovus and QRC ) for the analysis, including library characterization, delay models, and clock definitions
• Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics. Ensure that the design meets timing requirements for various corners and operating conditions (e.g., process, voltage, temperature variations).
• Identify and analyze asynchronous signals crossing between different clock domains to ensure proper synchronization and to avoid metastability issues.
• Define and analyze multicycle paths and false paths to accurately capture the designs timing constraints.
• Collaborate with RTL and physical design teams to achieve timing closure by optimizing the design or constraints. Perform incremental and formal ECO (Engineering Change Order) analysis to address timing issues.
• Work with CTS engineers to ensure that the clock tree meets timing requirements and minimizes clock skew and jitter.
• Perform post-layout STA to account for parasitic capacitance and resistance effects introduced during the physical design phase. 
• Identify and resolve timing violations and sign-off on the final timing closure.
• Analyze timing margins to account for variability and manufacturing process variations, ensuring robust operation.
• Prepare detailed timing analysis reports, including timing paths, violations, and suggestions for timing optimization.
• Collaborate closely with RTL designers, physical designers, DFT (Design for Test) engineers, and verification teams to resolve timing-related issues.
• Contribute to the development and improvement of STA methodologies and flows to enhance efficiency and accuracy.
  Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Vietnam are the preferred work locations 
• Preferred resources with valid regional work permit.