EMBEDDED : SOFTWARE APPLICATION DEVELOPER

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Work Location  : Bangalore

Work Expertise : 1 - 2 years

Job Specs         :      

• B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering.
• Expertise in embedded C programming
• Expertise in C++ programming
• Expertise in python scripting
• Certification in embedded software application development from premier training institutes.

NOTE : Must be willing to work onsite at ITPL

Work Location  : Canada, Remote

Work Expertise : 6 -10 years

Job Specs         :      

• B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering.
• Expertise in high performance analog layout in advance CMOS process nodes
• Expertise in layouts of high performance and high speed analog blocks ( ADC, DAC, PLL )
• Expertise in high speed SERDES is mandatory
• Expertise in analog layout techniques such as common centroid, interdigitation, shielding, dummy devices, EM aware routing on critical block, and must be versed with with VXL compliant methodology
• Expertise in physical verification checks DRC, LVS, DFM, ERC, EM, IR etc.
• Expertise in layout automation using SKILL / PERL / Python 
• VISA SPONSORED

Work Location  : Arizona, Bangalore, Beijing, Taiwan, Vietnam

Work Expertise : 3 - 10 years

Desired Profile  :      

• B.E./ B.Tech or M.E./ M.Tech in Electronics, Electrical, or VLSI Engineering.
• Collaborate with design teams to identify verification needs and propose coverage-driven solutions
• Expertise in developing advanced bespoke verification flows
• Expertise with analog, mixed-signal and RF circuit verification including behavioral modeling, simulation, and validation.
• Expertise in Verilog-A, Verilog-AMS and System Verilog real number modeling for mixed-signal verification.
• Expertise in industry-standard analog / mixed-signal verification tools (Cadence Virtuoso, Spectre, ADE-XL, VCS, Xcelium)
• Expertise in real-number emulation on the Cadence Palladium or Synopsys ZeBu platforms
• Expertise in creating behavioral models of analog and RF components in System Verilog, Verilog-A, Verilog-AMS and other relevant modeling languages
• Expertise in writing test benches and validation plans to ensure seamless integration between analog and digital subsystems
• Expertise in development and implementation of analog / mixed-signal verification methodologies for high-performance analog, mixed-signal, and RF circuits including DACs / ADCs, PLLs, LNAs and VGAs
• Expertise in performing functional and mixed-signal verification using industry-standard analog / mixed-signal simulation tools 
• Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations 
• Preferred resources with valid regional work permit

Work Location  : Bangalore

Work Expertise : 5 -10 years

Job Specs         :      

• B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering.
• Expertise in ASIC emulation / prototyping using Cadence / Synopsys tool flows
• Expertise in SOC / Subsystem / Graphics IP Emulation 
• Expertise in Palladium / Veloce / Zebu tools
• Expertise in System Verilog & Verilog language semantics and compilation flows
• Expertise in PCIe / USB protocol
• Expertise in X86 cores
• Good Knowledge on SOC architecture

Work Location  : Shanghai*, Singapore**

Work Expertise : 5 -10 years

Job Specs         :      

• Expertise in physical design implementation of large ASICs (100 to 400 million gates complexity).
• Expertise in technical hands-on competency in using leading edge physical design EDA tools in projects. (Cadence tool) 
• Expertise in CPU / DSP architecture / algorithm
• Expertise in top end physical design implementation
• Expertise in EDA tools for the design and implementation of 100 ~ 400 million gate integrated circuits in 12nm* / 7nm* / 5nm / 3nm / 2nm process technologies
• Expertise in one or more VLSI design tools for Place & Route, verilog simulation, DRC/LVS verification, timing analysis, scripting languages
• Expertise in Linux / Unix scripting.
• Citizens of Malaysia, Singapore and Vietnam are only considered for this requirement**
• Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Shanghai is your preferred work locations* 
• VISA SPONSORED

Work Location  : Bangalore, Beijing, Moscow, Romania, Vietnam

Work Expertise : 8+ years

Job Specs         :      

• Expertise in ASIC RTL Design
• Expertise in ASIC IP Design
• Expertise in CDC and Lint tools
• Expertise in design and simulation tools
• Expertise in Video processing algorithms / interfaces
• Expertise in CXL / PCIe Protocol, 5G, Datacenter
• Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Vietnam are the preferred work locations 
• Preferred resources with valid regional work permit.

Work Location  : Bangalore, Beijing, Dallas, Malaysia, Pune, Romania, Taiwan

Work Expertise : 4+ years

Job Specs         :      

• Expertise in Digital Verification 
• Expertise in Functional Verification 
• Expertise in SOC / IP Verification
• Expertise in working on system Verilog assertions & test benches
• Expertise in working on OVM / UVM / VMM based verification flow
• Expertise in working on ARM processor
• Expertise in working on AMBA bus protocols  (AXI, AHB, APB) 
• Expertise in CXL or PCIe Protocol Verification
• Expertise in simulation tools (VCS, ModelSim, Questa)
• Expertise in driving Verification Strategy, writing Test Plan, developing Test Bench, Test cases.
• Expertise in analysing Code Coverage, Functional Coverage and Assertions.
• Expertise in verification of complex SoCs.
• Expertise in Test Plan creation and Verification technologies like Code Coverage, Functional coverage, assertion based verification.
• Expertise in Verification of complex datapath, DSP based ASICs 
• Expertise in MAC Protocol: USB, WiFi , Bluetooth , PCIe is mandatory 
• Good knowledge in gate-level simulation, and Scripting languages like Python, TCL
• Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan are the preferred work locations 
• Preferred resources with valid regional work permit.

Work Location  : Bangalore, Beijing, Moscow, Taiwan, Vietnam

Work Expertise : 6 - 12 years 

Desired Profile  :       

• Expertise in ASIC PD.
• Expertise in digital physical design
• Expertise in working with 3nm & 5nm technology nodes 
• Expertise in EDA synthesis, APR, STA tools and methodologies
• Expertise in one or more of the following tools ICC, ICC2, Innovus, Olympus
• Working knowledge of one or more of the following tools Primetime, Calibre, and Red hawk
• Expertise in working with multi modes and multi corners STA
• Working Knowledge of multiple power planes and multiple VT libraries
• Basic domain knowledge of EM, IR, RV analysis, Noise and Formal Equivalence Verification
• Good at scripting languages PERL, TCL, shell
• Worked on at least 2 tape ins of moderate to high speed designs with multiple power planes
• Debug, fix, and validate pre- and post-silicon IP/sub-system logic issues and bugs
• Expertise in one or more of the following circuit design fields is an advantage: clock tree optimization, Timing analysis, and Power optimization
• Expertise in making ECOs both Metal and logic level ecos
• Expertise in DRC and LVS cleanup of designs during sign off
• Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations 
• Preferred resources with valid regional work permit

Work Location  : REMOTE - HYBRID

Work Expertise : 5+ years

Job Specs         :      

• Must be a resident of India, preferably in Bangalore or Pune
• Expertise in Digital Verification 
• Expertise in MAC Protocol: USB, WiFi , Bluetooth
• Expertise in SOC / IP Verification
• Expertise in working on system Verilog assertions & test benches
• Expertise in working on OVM / UVM / VMM based verification flow
• Good knowledge in gate-level simulation, and Scripting languages like Python, TCL

Work Location  : Bangalore, Bhubaneswar, Bihar, Kolkata, Kochi, Mysore

Work Expertise : 10+ years

Desired Profile  :       

• Bachelor's / Master's degree in engineering from EEE / E&C 
• Expertise in managing and leading technical teams across different continents 
• Expertise in leading business strategy in the VLSI / Semiconductor Services / foundry business industry 
• Expertise in managing end to end projects including tape outs
• Must be willing to travel at short notice, relocate as per business needs 
• Must be willing to work onsite (customer premises) as per business needs
• Expertise in working on any of the following technologies is mandatory :

1. ANALOG MIXED SIGNAL LAYOUT - finfet / high speed / planar technology nodes
2. ANALOG DESIGN - data converter / power management / pll
3. ANALOG VERIFICATION
4. ASIC PHYSICAL DESIGN
5. ASIC RTL DESIGN 
6. DFT DESIGN - jtag / mbist / lbist / scan
7. DIGITAL VERIFICATION - OVM / UVM / VMM
8. EDA CAD FLOW - tcl / primetime / design compiler

Job Specs         :       

• Responsible for meeting delivery, revenue, operational, customer satisfaction targets and team management
• Hire and manage high caliber technical teams across GCC, ODC and onsite
• Develop, Drive high quality business / technology strategy and oversee the translation of this strategy into tactical action
• Uphold the organization's culture and long term missions
• Liaise and negotiate with various partners around the world to bring in new partnership.
• Synergize all company's resources and talents for the growth of company's business
• Oversee all sectors and fields of the business to ensure the company's competitiveness
• Provide leadership, direction, major decision making and resolution support to operations, projects and staff.
• Build strategic business partnerships and execute these opportunities through collaboration with external partners 

Work Location  : Bangalore, Beijing, Moscow, Noida, Vietnam

Work Expertise : 7 - 12 years

Job Specs         :      

• Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design.
• Set up and configure STA tools ( PrimeTime, StarRC, Tempus, Innovus and QRC ) for the analysis, including library characterization, delay models, and clock definitions
• Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics. Ensure that the design meets timing requirements for various corners and operating conditions (e.g., process, voltage, temperature variations).
• Identify and analyze asynchronous signals crossing between different clock domains to ensure proper synchronization and to avoid metastability issues.
• Define and analyze multicycle paths and false paths to accurately capture the designs timing constraints.
• Collaborate with RTL and physical design teams to achieve timing closure by optimizing the design or constraints. Perform incremental and formal ECO (Engineering Change Order) analysis to address timing issues.
• Work with CTS engineers to ensure that the clock tree meets timing requirements and minimizes clock skew and jitter.
• Perform post-layout STA to account for parasitic capacitance and resistance effects introduced during the physical design phase. 
• Identify and resolve timing violations and sign-off on the final timing closure.
• Analyze timing margins to account for variability and manufacturing process variations, ensuring robust operation.
• Prepare detailed timing analysis reports, including timing paths, violations, and suggestions for timing optimization.
• Collaborate closely with RTL designers, physical designers, DFT (Design for Test) engineers, and verification teams to resolve timing-related issues.
• Contribute to the development and improvement of STA methodologies and flows to enhance efficiency and accuracy.
  Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Vietnam are the preferred work locations 
• Preferred resources with valid regional work permit.