SEMICONDUCTOR : ANALOG CIRCUIT DESIGN ENGINEER

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Work Location  : Noida

Work Expertise : 5 - 10 years

Job Specs         :        

• Bachelor's / Master's degree in engineering from EEE / E&C with expertise in mixed-signal or CMOS circuit design
• Expertise in analog blocks like power management DC-DC convertor, LDOs 
• Expertise in designing ADC / DAC/ PLLs or Experience in simulation or characterization of IO cells
• Design and architect CMOS analog and mixed-signal integrated circuits
• Simulate designs with state-of-the-art CAD tools
• Document designs and simulation results 
• Experience with high-speed SERDES circuits
• Knowledge of layout issues
• Experience with circuit simulators (HSPICE, Spectre, etc)
• Experience with Cadence Design Environment is an asset
• Working knowledge of PERL and UNIX shell scripting languages is an asset

Work Location  : Remote / Work from Anywhere / Moonlighting

Work Expertise : 7 - 15 years

Job Specs         :        

• Bachelor's / Master's degree in engineering from EEE / E&C with expertise in managing and mentoring memory circuit design teams across multi polar world.
• Expertise in custom memory circuit design implementations
• Expertise in memory design flow Architecture, circuit design, Layout implementation, Characterization, Model generation 
• Expertise in validation of the characterized data and custom instances data
• Expertise in generation of timing views (.libs), validation and quality checks 
• Expertise in behavior modelling of memories and verification 
• Expertise in advanced technology nodes is preferable
• Strong knowledge in SRAM architecture, Critical Path Modelling, Margin analysis and full configuration analysis, and Monte Carlo simulations.
• Good understanding of layout design aspects in lower process nodes and their impact on circuit performance 
• Resource must be a citizen of India residing across any states / UT's of India

Work Location  : Bangalore

Work Expertise : 4 - 8 years

Job Specs         :        

• Expertise in baremetal firmware development in Pre Silicon 
• Expertise in writing test benches in UVM methodology
• Expertise in debugging firmware using Verdi / Sim Vision along with RTL
• Expertise in signal tracing in Verilog
• Expertise in High-Speed Serial I/F - PHY 
• Expertise in UCIe, PCIe, CXL, HBM, Qlink (Qualcomm), DigRF (MIPI)
• Expertise working in Linux as host environment 
• Expertise in git as version control system· 
• Expertise in Jenkins based automation would be a plus.
• Expertise in Triaging includes issues : Coming out of internal Jenkins/Manual regressions as well as external
• Expertise in reading the UCIe specs
• Expertise in filtering out noise (environment / setup / known issues)
• Expertise in triage bit deeper, classifying issue as new belonging to one of : Test Case / Environment or firmware or RTL 
• Expertise in solving firmware issues / ENH from specs / test coverage /  automation

Work Location  : Bangalore

Work Expertise : 1 - 2 years

Job Specs         :      

• B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering.
• Expertise in embedded C programming
• Expertise in C++ programming
• Expertise in python scripting
• Certification in embedded software application development from premier training institutes.

NOTE : Must be willing to work onsite at ITPL

Work Location  : Noida

Work Expertise : 7 -10 years

Job Specs         :      

• B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering.
• Expertise in electrical circuit analysis, design, and test fundamentals
• Expertise in automation of Analog Characterization Setups using Labview and Test Stand
• Expertise in debug and problem solving skills
• Expertise in Silicon bring up & Analog Validation Platforms like Analog Board for new ASIC/SoC design
• Expertise in bench characterization challenges on stand-alone /automated bench setup
• Expertise in C programming
• Expertise in using test & measurement equipments used in Analog Validation (High Speed DSA, Programmable Voltage/Current Sources and Measurement equipments, AWG, Spectrum Analyzer, Audio precision etc)
• Expertise with PVT characterization of Analog IP's ADC, DAC,PLL,USB,VREG, OSC,DDR, LOW POWER and IO PAD's
• Good debugging exposure and root cause analysis for new analog designs
• Knowledge for Multilayer Board design, testing, integration and Signal Integrity issues.
• Some understanding of differential signaling, transmission line theory.
• Experience with LabVIEW and Test Stand automation software
• Experience in a lab environment
• Develop unique and sometimes complex bench characterization test methodologies for ADC,DAC,PLL,USB, VREG, OSC,DDR, LOW POWER and IO PADs in order to determine and verify the device’s functional and electrical 
• performance across Manufacturing Process, Voltage, and Temperature combinations for the datasheet parameters
• Develop and write automated code to control all test equipment during the collection and processing of characterization data which can run automatically to generate required PVT electrical parameters.
• Perform Design Evaluation and Bench Characterization for Analog IPs on devices still in development servicing the Automotive, Industrial and Select Consumer Electronics industries 
• Provide requirements, review schematics and PCB layout to develop circuit boards that maintain excellent Signal Integrity to enable design evaluation and characterization of ADC,DAC,PLL,USB,VREG, OSC,DDR, LOW POWER and IO PADs
• Provide customer application note support by generating characterization data for customer scenario
• Participate with a team consisting of marketing, systems, design, test, and project management to support the successful launch of new products

Work Location  : Bangalore, Canada, Hyderabad, Noida, Remote

Work Expertise : 3 -10 years

Job Specs         :      

• B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering.
• Expertise in high performance analog layout in advance CMOS process nodes
• Expertise in layouts of high performance and high speed analog blocks ( ADC, DAC, PLL )
• Expertise in high speed SERDES is mandatory
• Expertise in analog layout techniques such as common centroid, interdigitation, shielding, dummy devices, EM aware routing on critical block, and must be versed with with VXL compliant methodology
• Expertise in physical verification checks DRC, LVS, DFM, ERC, EM, IR etc.
• Expertise in layout automation using SKILL / PERL / Python 
• Bangalore : 5 - 10 years of relevant expertise 
• Canada & Remote : 6 -10 years of relevant expertise
• Hyderabad : 4 -10 years of relevant expertise
• Noida        : 3 - 5 years of relevant expertise 
• REMOTE : Resource must be a citizen of India residing across any states / UT's of India
• VISA SPONSORED

Work Location  : Arizona, Bangalore, Beijing, Taiwan, Vietnam

Work Expertise : 3 - 10 years

Desired Profile  :      

• B.E./ B.Tech or M.E./ M.Tech in Electronics, Electrical, or VLSI Engineering.
• Collaborate with design teams to identify verification needs and propose coverage-driven solutions
• Expertise in developing advanced bespoke verification flows
• Expertise with analog, mixed-signal and RF circuit verification including behavioral modeling, simulation, and validation.
• Expertise in Verilog-A, Verilog-AMS and System Verilog real number modeling for mixed-signal verification.
• Expertise in industry-standard analog / mixed-signal verification tools (Cadence Virtuoso, Spectre, ADE-XL, VCS, Xcelium)
• Expertise in real-number emulation on the Cadence Palladium or Synopsys ZeBu platforms
• Expertise in creating behavioral models of analog and RF components in System Verilog, Verilog-A, Verilog-AMS and other relevant modeling languages
• Expertise in writing test benches and validation plans to ensure seamless integration between analog and digital subsystems
• Expertise in development and implementation of analog / mixed-signal verification methodologies for high-performance analog, mixed-signal, and RF circuits including DACs / ADCs, PLLs, LNAs and VGAs
• Expertise in performing functional and mixed-signal verification using industry-standard analog / mixed-signal simulation tools 
• Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations 
• Preferred resources with valid regional work permit

Work Location  : Bangalore, Hyderabad, Israel, Moscow

Work Expertise : 5 -10 years

Job Specs         :      

• Expertise in physical design implementation of large ASICs (100 to 400 million gates complexity).
• Expertise in technical hands-on competency in using leading edge physical design EDA tools in projects. (Cadence tool) 
• Expertise in CPU / DSP architecture / algorithm
• Expertise in top end physical design implementation
• Expertise in EDA tools for the design and implementation of 100 ~ 400 million gate integrated circuits in 12nm* / 7nm* / 5nm / 3nm / 2nm process technologies
• Expertise in one or more VLSI design tools for Place & Route, verilog simulation, DRC/LVS verification, timing analysis, scripting languages
• Expertise in Linux / Unix scripting.
• Preferred resources with valid regional work permit.

Work Location  : Bangalore, Beijing, Moscow, Romania, Vietnam

Work Expertise : 8+ years

Job Specs         :      

• Expertise in ASIC RTL Design
• Expertise in ASIC IP Design
• Expertise in CDC and Lint tools
• Expertise in design and simulation tools
• Expertise in Video processing algorithms / interfaces
• Expertise in CXL / PCIe Protocol, 5G, Datacenter
• Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Vietnam are the preferred work locations 
• Preferred resources with valid regional work permit.

Work Location  : Bangalore, Beijing, Dallas, Pune, Romania, Taiwan

Work Expertise : 3 - 15 years

Job Specs         :      

• Expertise in Digital Verification 
• Expertise in Functional Verification 
• Expertise in SOC / IP Verification
• Expertise in working on system Verilog assertions & test benches
• Expertise in working on OVM / UVM / VMM based verification flow
• Expertise in working on ARM processor
• Expertise in working on AMBA bus protocols  (AXI, AHB, APB) 
• Expertise in CXL or PCIe Protocol Verification
• Expertise in simulation tools (VCS, ModelSim, Questa)
• Expertise in driving Verification Strategy, writing Test Plan, developing Test Bench, Test cases.
• Expertise in analysing Code Coverage, Functional Coverage and Assertions.
• Expertise in verification of complex SoCs.
• Expertise in Test Plan creation and Verification technologies like Code Coverage, Functional coverage, assertion based verification.
• Expertise in Verification of complex datapath, DSP based ASICs 
• 3+ years of expertise in PCIe & AXi  protocols and ethernet Protocol or sub system verification is mandatory for Bangalore requirement
• 4+ years of expertise in MAC Protocol: USB, WiFi  is mandatory for Pune requirement
• Good knowledge in gate-level simulation, and Scripting languages like Python, TCL
• Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan are the preferred work locations 
• Preferred resources with valid regional work permit.

Work Location  : Remote / Work from Anywhere

Work Expertise : 5+ years

Job Specs         :      

• Must be a resident of India, preferably in Bangalore or Pune
• Expertise in Digital Verification 
• Expertise in MAC Protocol: USB, WiFi , Bluetooth
• Expertise in SOC / IP Verification
• Expertise in working on system Verilog assertions & test benches
• Expertise in working on OVM / UVM / VMM based verification flow
• Good knowledge in gate-level simulation, and Scripting languages like Python, TCL
• REMOTE : Resource must be a citizen of India residing across any states / UT's of India

Work Location  : Bangalore, Bhubaneswar, Bihar, Kolkata, Kochi, Mysore

Work Expertise : 10+ years

Desired Profile  :       

• Bachelor's / Master's degree in engineering from EEE / E&C 
• Expertise in managing and leading technical teams across different continents 
• Expertise in leading business strategy in the VLSI / Semiconductor Services / foundry business industry 
• Expertise in managing end to end projects including tape outs
• Must be willing to travel at short notice, relocate as per business needs 
• Must be willing to work onsite (customer premises) as per business needs
• Expertise in working on any of the following technologies is mandatory :

1. ANALOG MIXED SIGNAL LAYOUT - finfet / high speed / planar technology nodes
2. ANALOG DESIGN - data converter / power management / pll
3. ANALOG VERIFICATION
4. ASIC PHYSICAL DESIGN
5. ASIC RTL DESIGN 
6. DFT DESIGN - jtag / mbist / lbist / scan
7. DIGITAL VERIFICATION - OVM / UVM / VMM
8. EDA CAD FLOW - tcl / primetime / design compiler

Job Specs         :       

• Responsible for meeting delivery, revenue, operational, customer satisfaction targets and team management
• Hire and manage high caliber technical teams across GCC, ODC and onsite
• Develop, Drive high quality business / technology strategy and oversee the translation of this strategy into tactical action
• Uphold the organization's culture and long term missions
• Liaise and negotiate with various partners around the world to bring in new partnership.
• Synergize all company's resources and talents for the growth of company's business
• Oversee all sectors and fields of the business to ensure the company's competitiveness
• Provide leadership, direction, major decision making and resolution support to operations, projects and staff.
• Build strategic business partnerships and execute these opportunities through collaboration with external partners 

Work Location  : Noida

Work Expertise : 3 - 6 years 

Job Specs         :      

• Expertise with block level timing constraints enablement & analysis
• Expertise in PrimeTime & PT-ECO 
• Expertise with clocking & data flow understanding ;
• Expertise in reviewing check timing and constraints QoR checks 
• Expertise with constraints validation understanding ;
• Expertise with CTS building
• Expertise with clock tree spec review  / closure 
• Expertise in timing ECOs & Final Timing last mile closure at block level
• Expertise in TCL, Unix scripting

Work Location  : Bangalore, Beijing, Hyderabad, Moscow, Taiwan, Vietnam

Work Expertise : 6 - 12 years 

Desired Profile  :       

• Expertise in ASIC PD.
• Expertise in digital physical design
• Expertise in working with 3nm & 5nm technology nodes 
• Expertise in EDA synthesis, APR, STA tools and methodologies
• Expertise in one or more of the following tools ICC, ICC2, Innovus, Olympus
• Working knowledge of one or more of the following tools Primetime, Calibre, and Red hawk
• Expertise in working with multi modes and multi corners STA
• Working Knowledge of multiple power planes and multiple VT libraries
• Basic domain knowledge of EM, IR, RV analysis, Noise and Formal Equivalence Verification
• Good at scripting languages PERL, TCL, shell
• Worked on at least 2 tape ins of moderate to high speed designs with multiple power planes
• Debug, fix, and validate pre- and post-silicon IP/sub-system logic issues and bugs
• Expertise in one or more of the following circuit design fields is an advantage: clock tree optimization, Timing analysis, and Power optimization
• Expertise in making ECOs both Metal and logic level ecos
• Expertise in DRC and LVS cleanup of designs during sign off
• Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations 
• Preferred resources with valid regional work permit

Work Location  : Bangalore, Beijing, Moscow, Noida,  Vietnam

Work Expertise : 7 - 12 years 

Job Specs         :      

• Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design.
• Set up and configure STA tools ( PrimeTime, StarRC, Tempus, Innovus and QRC ) for the analysis, including library characterization, delay models, and clock definitions
• Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics. Ensure that the design meets timing requirements for various corners and operating conditions (e.g., process, voltage, temperature variations).
• Identify and analyze asynchronous signals crossing between different clock domains to ensure proper synchronization and to avoid metastability issues.
• Define and analyze multicycle paths and false paths to accurately capture the designs timing constraints.
• Collaborate with RTL and physical design teams to achieve timing closure by optimizing the design or constraints. Perform incremental and formal ECO (Engineering Change Order) analysis to address timing issues.
• Work with CTS engineers to ensure that the clock tree meets timing requirements and minimizes clock skew and jitter.
• Perform post-layout STA to account for parasitic capacitance and resistance effects introduced during the physical design phase. 
• Identify and resolve timing violations and sign-off on the final timing closure.
• Analyze timing margins to account for variability and manufacturing process variations, ensuring robust operation.
• Prepare detailed timing analysis reports, including timing paths, violations, and suggestions for timing optimization.
• Collaborate closely with RTL designers, physical designers, DFT (Design for Test) engineers, and verification teams to resolve timing-related issues.
• Contribute to the development and improvement of STA methodologies and flows to enhance efficiency and accuracy.
  Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Vietnam are the preferred work locations 
• Preferred resources with valid regional work permit.