SEMICONDUCTOR : ASIC PHYSICAL DESIGN ENGINEER

NEW REQUIREMENT

Work Location : Bangalore, Beijing, Moscow, Noida, Taiwan, Vietnam

Work Expertise : 3 - 5 years

Desired Profile :

Expertise in ASIC PD.
Expertise in digital physical design
Expertise in working with 3nm & 5nm technology nodes
Expertise in EDA synthesis, APR, STA tools and methodologies
Expertise in one or more of the following tools ICC, ICC2, Innovus, Olympus
Working knowledge of one or more of the following tools Primetime, Calibre, and Red hawk
Expertise in working with multi modes and multi corners STA
Working Knowledge of multiple power planes and multiple VT libraries
Basic domain knowledge of EM, IR, RV analysis, Noise and Formal Equivalence Verification
Good at scripting languages PERL, TCL, shell
Worked on at least 2 tape ins of moderate to high speed designs with multiple power planes
Debug, fix, and validate pre- and post-silicon IP/sub-system logic issues and bugs
Expertise in one or more of the following circuit design fields is an advantage: clock tree optimization, Timing analysis, and Power optimization
Expertise in making ECOs both Metal and logic level ecos
Expertise in DRC and LVS cleanup of designs during sign off
Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations
Preferred resources with valid regional work permit

SEMICONDUCTOR : ASIC RTL & IP LOGIC DESIGN ENGINEER

NEW REQUIREMENT

Work Location : Bangalore, Beijing, Moscow, Romania, Vietnam

Work Expertise : 8+ years

Job Specs :

Expertise in ASIC RTL Design
Expertise in ASIC IP Design
Expertise in CDC and Lint tools
Expertise in design and simulation tools
Expertise in Video processing algorithms / interfaces
Expertise in CXL / PCIe Protocol, 5G, Datacenter
Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Vietnam are the preferred work locations
Preferred resources with valid regional work permit.

SEMICONDUCTOR : DIGITAL VERIFICATION ENGINEER

NEW REQUIREMENT

Work Location : REMOTE - HYBRID

Work Expertise : 4+ years

Job Specs :

Must be a resident of India, preferably in Bangalore or Pune
Expertise in Digital Verification
Expertise in MAC Protocol: USB, WiFi , Bluetooth , PCIe
Expertise in SOC / IP Verification
Expertise in working on system Verilog assertions & test benches
Expertise in working on OVM / UVM / VMM based verification flow
Good knowledge in gate-level simulation, and Scripting languages like Python, TCL

SEMICONDUCTOR : GLS VERIFICATION ENGINEER

NEW REQUIREMENT

Work Location : Bangalore, Beijing, Moscow, Romania, Taiwan, Vietnam

Work Expertise : 5 - 10 years

Desired Profile :

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or VLSI Engineering.
Expertise in execution and debugging of test-suites at the GPU sub-system level
Expertise in GLS (Gate-Level Simulation)
Expertise in writing assertions and test benches using system verilog
Expertise in UVM methodologies
Expertise in Test planning
Expertise in sub-system level DV
Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Taiwan and Vietnam are the preferred work locations
Preferred resources with valid regional work permit

SEMICONDUCTOR : STA & SYNTHESIS ENGINEER

NEW REQUIREMENT

Work Location : Bangalore, Beijing, Moscow, Noida, Vietnam

Work Expertise : 3 - 5 years

Job Specs :

Work with design and architecture teams to define and generate timing constraints that specify the desired timing requirements for the design.
Set up and configure STA tools ( PrimeTime, StarRC, Tempus, Innovus and QRC ) for the analysis, including library characterization, delay models, and clock definitions
Perform static timing analysis to evaluate setup and hold times, clock-to-q delays, and other timing metrics. Ensure that the design meets timing requirements for various corners and operating conditions (e.g., process, voltage, temperature variations).
Identify and analyze asynchronous signals crossing between different clock domains to ensure proper synchronization and to avoid metastability issues.
Define and analyze multicycle paths and false paths to accurately capture the designs timing constraints.
Collaborate with RTL and physical design teams to achieve timing closure by optimizing the design or constraints. Perform incremental and formal ECO (Engineering Change Order) analysis to address timing issues.
Work with CTS engineers to ensure that the clock tree meets timing requirements and minimizes clock skew and jitter.
Perform post-layout STA to account for parasitic capacitance and resistance effects introduced during the physical design phase.
Identify and resolve timing violations and sign-off on the final timing closure.
Analyze timing margins to account for variability and manufacturing process variations, ensuring robust operation.
Prepare detailed timing analysis reports, including timing paths, violations, and suggestions for timing optimization.
Collaborate closely with RTL designers, physical designers, DFT (Design for Test) engineers, and verification teams to resolve timing-related issues.
Contribute to the development and improvement of STA methodologies and flows to enhance efficiency and accuracy.
Expert level proficiency (Oral + Written) in Chinese language is mandatory incase Beijing, Vietnam are the preferred work locations
Preferred resources with valid regional work permit.