ACTIVE REQUIREMENTS

Work Location          : Bangalore 

Relevant Expertise : 10 - 13 Yrs 

Desired Profile         :      

•  CA with 10+ years of relevant experience in Assurance working with mid size audit firms
• Possess strong domain knowledge, understanding of business processes and possible risks in operations of at least one industry sector
• Effective use of Audit Tools
• Experience in IND AS / IFRS Assignments and handled large Statutory Audits
• Ability to identify risks in business processes
   

Work Location          : Bangalore 

Relevant Expertise : 3 - 5 Yrs 

Desired Profile         :      

• Qualified CA with 3+ years of post qualification experience in indirect taxation with mid size audit firms
•  Expertise in GST 
• Expertise in Advisory and Litigation

Work Location          : Bangalore, Penang 

Relevant Expertise : 3 - 8 Yrs 

Desired Profile         :      

• Expertise in CMOS / RF analog circuit design
• Expertise in designing analog building blocks like op-amps,  band gaps, differential amplifiers, LDO, high speed TX and RX,  equalizers etc
• Must have worked on Analog and or Digital PLLs for frequency  synthesis and/or SerDes applications 
• Must have worked on Charge pump, loop filter, VCO/DCO,  PFD/TDC, high speed dividers, PLL Loop Dynamics, Jitter sources  and modeling (RJ & DJ)
• Ability to take a design, perform schematic to post layout  verification, sign-off to post silicon bring up 

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Work Location          : Penang 

Relevant Expertise : 3 - 8 Yrs 

Desired Profile         :      

• Expertise in Analog and Mixed Signal Layout Blocks like PLL, RX, Tx, OPAMP 
• Expertise in Finfet Layout and Multipattern Metal Rules 
• Experience in SerDes PHY Layouts is an added advantage
• Must have worked on 3nm, 5nm, 7nm or 10nm nodes 

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Work Location          : Bangalore , Penang

Relevant Expertise : 3 - 10 Yrs 

Desired Profile         :       

• Expertise in physical design, IP integration and large chip  integration working with 16nm, 12nm & 7nm process
• Expertise with hierarchical design approach, top-down design,  budgeting, timing and physical convergence 
• Expertise in all aspects of ASIC design flows all aspects  including Floor planning, Clock & Power distribution, global  signal planning, I/O planning, hard IP integration
• Expertise in P&R flows, global timing verification, Physical  Design Verification Flows. 
• Must have worked on SoC issues such as multiple voltage and clock domains, ESD strategies, mixed signal block  integration, and package interactions 

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Work Location          : Bangalore , Hyderabad

Relevant Expertise : 4 - 10 Yrs 

Desired Profile         :       

• Expertise in SOC/ IP / System level Verification expertise with  test plan development, test bench coding
• Must have worked with protocols such as PCIe, AMBA Bus  (AXI, AHB, APB), DDR3/4/5/LPDDR etc
• Expertise in logic verification with exceptionally good  debugging skill
• Expertise in directed test and constrained randomized test  development
• Expertise in code coverage and functional coverage analysis
• Expertise in C, System Verilog, UVM/OVM 

Work Location          : Bangalore 

Relevant Expertise : 2 - 4 Yrs 

Desired Profile         :       

• Expertise in Custom layout, especially Memory Layout design (RAM, ROM, SRAM).
• Memory Leafcell layout design from scratch till top level integration.
• Good knowledge on different types of memory architecture.
• Good knowledge in optimized layout design for better performance.

Work Location          : Bangalore, Penang 

Relevant Expertise : 3 - 8 Yrs 

Desired Profile         :      

• Expertise in Logic design or micro-architecture or RTL coding for design and integration of complex multi clock domain Designs
• Experience in Verilog or System-Verilog with knowledge of AMBA, AXI, AHB, APB, Ethernet, USB, H264, H265, clocking or reset or debug architecture
• Experience in Multi Clock designs, Asynchronous interface, Constraint development & Timing Closure
• Experience in using the tools in ASIC development such as Lint, CDC, Design compiler and Primetime is required. Experience in Low power design , Synthesis and timing concepts for ASIC
• Experience in creating pad ring and working with the chip level floorplan team is an added advantage  

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