SEMICONDUCTOR : DESIGN ENGINEER (M.TECH - FRESHER)

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Employment Type  : Full time - Permanent

Work Location        : Bangalore 

Work Expertise       : 0 Years - 0 Years

Desired Profile        :        

• Bachelor's / Master's degree in engineering from EEE / E&C / VLSI with more than 75% or 7.9 CGPA in Engineer
• The candidate must have completed BE in 2022 / 2023 
• The candidate must have completed M.Tech in 2025 / 2026  
• Must be ready to work on analog layout

Employment Type   : Full time - Permanent

Work Location         : Bangalore 

Work Expertise        : 15 Years - 20 Years

Desired Profile         :        

• Bachelor's / Master's degree in engineering from EEE / E&C with expertise in mixed-signal or CMOS circuit design
• Expertise with high-speed SERDES circuits is mandatory
• Expertise in analog blocks like power management DC-DC convertor, LDOs 
• Expertise in designing ADC / DAC/ PLLs or Experience in simulation or characterization of IO cells
• Design and architect CMOS analog and mixed-signal integrated circuits
• Simulate designs with state-of-the-art CAD tools
• Document designs and simulation results 
• Knowledge of layout issues
• Expertise with circuit simulators (HSPICE, Spectre, etc)
• Expertise with Cadence Design Environment is an asset
• Expertise in PERL and UNIX shell scripting languages
• Expertise in managing end to end projects including tape outs
• Must be willing to work onsite (customer premises) as per business needs.
• Must be an Indian Citizen residing in any state or union territories of India 
• Must be also willing to work as an individual; contributor based on business need

Employment Type  : Full time - Permanent

Work Location         : Bangalore, Chennai, Japan, Malaysia, Vietnam 

Work Expertise        : 5 Years - 15 Years

Desired Profile         :        

• Bachelor's / Master's degree in engineering from EEE / E&C with expertise in ASIC DFT
• Define and implement DFT architecture for SoC / ASIC designs
• Perform scan insertion and scan chain stitching
• Develop and validate ATPG patterns for stuck-at, transition, bridge, and path delay faults
• Implement and verify MBIST / memory repair solutions
• Perform DFT rule checks (DRC) and resolve violations
• Support JTAG / boundary scan / IEEE 1149.1 implementation
  Run and debug Gate Level Simulations (GLS) for DFT patterns
• Analyze and improve test coverage, pattern count, and test time
• Work closely with design, verification, physical design, and silicon validation teams
• Support post-silicon bring-up and failure analysis
• Create DFT documentation, methodology, and best-practice flows.
• Duolingo is mandatory for Japan
• Preferred immediate hires

             VISA SPONSORED 

Employment Type  : Full time - Permanent

Work Location         : Bangalore, Cambridge, Hyderabad, Scotland

Work Expertise        : 8 Years - 15 Years

Desired Profile         :        

• Bachelor's / Master's degree in engineering from EEE / E&C with expertise in ASIC Verification or Digital Verification
• Expertise in VIP integration 
• Expertise in ARM process
• Expertise in DDR ( 4 or 5 controller with Phy) / Ethernet (100 G or 2002 G) / PCIe (Gen 5 or 6) protocol  
• Expertise in SOC / IP / sub-system level Verification
• Expertise in working on system Verilog assertions & test benches
• Expertise in working on OVM / UVM / VMM based verification flow
• Good knowledge in gate-level simulation, and Scripting languages like Python, TCL

Employment Type   : Full time - Permanent

Work Location         : Bangalore 

Work Expertise        : 10 Years - 20 Years

Desired Profile         :        

• Bachelor's / Master's degree in engineering from EEE / E&C with expertise in memory layout design
• Expertise in submicron processes - 7nm, 5nm, 3nm, 2nm
• Expertise in leading teams, hiring & mentoring junior engineers and manage projects effectively.
• Expertise in memory layout design and physical verification (LVS, DRC, ERC, Antenna, Electro Migration).
• Expertise in Cadence Layout tools (Virtuoso XL, VXL, or EXL) and Calibre verification tools.
• Expertise in floor-planning, hierarchy layout, and chip integration.
• Solid understanding of memory architecture and RC requirements, with the ability to plan signal and power routing.
• Strong knowledge of memory layout topology; experience with memory compilers is preferred.
• Knowledge of AI, layout automation, and script/SKILL programming is preferred.
• Ability to lead new technology reviews to document layout methodologies, flows, and guidelines.

Employment Type  : Full time - Permanent

Work Location        : Bangalore

Work Expertise       : 15+ years 

Desired Profile        :        

• Expertise in ASIC PD.
• Expertise in digital physical design
• Expertise in EDA synthesis, APR, STA tools and methodologies
• Expertise in one or more of the following tools ICC, ICC2, Innovus, Olympus
• Working knowledge of one or more of the following tools Primetime, Calibre, and Red hawk
• Expertise in working with multi modes and multi corners STA
• Working Knowledge of multiple power planes and multiple VT libraries
• Basic domain knowledge of EM, IR, RV analysis, Noise and Formal Equivalence Verification
• Good at scripting languages PERL, TCL, shell
• Expertise in EDA tools for the design and implementation of 100 ~ 400 million gate integrated circuits in 12nm* / 7nm* / 5nm / 3nm / 2nm process technologies
• Worked on at least 2 tape ins of moderate to high speed designs with multiple power planes
• Debug, fix, and validate pre- and post-silicon IP/sub-system logic issues and bugs
• Expertise in one or more of the following circuit design fields is an advantage: clock tree optimization, Timing analysis, and Power optimization
• Expertise in making ECOs both Metal and logic level
• Expertise in DRC and LVS cleanup of designs during sign off
• 15+ years of experience must include 10+ years of expertise in managing and leading ASIC PD technical teams across different continents 
• Expertise in leading business strategy in the VLSI / Semiconductor Services / foundry business industry 
• Expertise in managing end to end projects including tape outs
• Must be willing to travel at short notice, relocate as per business needs 
• Must be willing to work onsite (customer premises) as per business needs
• Prior expertise in scaling large teams in services industry for the same technical domain is mandatory

Job Specs  : 

• Responsible for meeting delivery, revenue, operational, customer satisfaction targets and team management
• Hire and manage high caliber technical teams across GCC, ODC and onsite
• Develop, Drive high quality business / technology strategy and oversee the translation of this strategy into tactical action
• Uphold the organization's culture and long term missions
• Liaise and negotiate with various partners around the world to bring in new partnership.
• Synergize all company's resources and talents for the growth of company's business
• Oversee all sectors and fields of the business to ensure the company's competitiveness
• Provide leadership, direction, major decision making and resolution support to operations, projects and staff.
• Build strategic business partnerships and execute these opportunities through collaboration with external partners

Employment Type: Full time - Permanent

Work Location      : Cambridge, Bangalore, London, Malaysia, San Jose

Work Expertise     : 5 Years - 15 Years

Desired Profile      :        

• Bachelor's / Master's degree in engineering from EEE / E&C with expertise in ASIC PD
• Experience in Top / Block level ASIC PnR implementation  (RTL to GDSII).
• Tape-out experience in lower nodes like 3nm, 5nm, 7nm, 10nm and above.
• Hands-on experience in Synthesis, Floor planning, Placement, Clock tree synthesis, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification (DRC/LVS/DFM, chip finishing) and Sign Off.
• Excellent communication and presentation skills, experience in collaborating with global teams.
• Experience in hierarchical designs and/or Low Power implementation is an advantage.
• Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics tool set.
• Must be an initiative-taker and be able to drive tasks independently and efficiently to completion.
• Ability to provide mentorship and guidance to junior engineers and be an effective team player.
• Expertise in Cadence Innovus, Tempus, Calibre
• Required relevant expertise for Malaysia is 5+ years and 10+ years of relevant expertise for other locations 
• Preferred immediate hires

             VISA SPONSORED FOR MALAYSIA

Employment Type  : Full time - Permanent

Work Location        : Bangalore, Cambridge, Malaysia, San Jose

Work Expertise       : 5 Years - 15 Years

Desired Profile  :        

• Bachelor's / Master's degree in engineering from EEE / E&C with expertise in ASIC STA / SYNTHESIS
• Timing analysis and logic synthesis of digital designs. 
• Achieve timing closure and optimize design performance, power and area.
• Perform RTL synthesis using industry-standard tools
• Should be capable to analyze and run LEC to ensure gate level netlist matches the original RTL
• Run Static Timing Analysis (STA) and identify timing violations
• Fix setup and hold violations across different corners/modes
• Work on constraints development (SDC creation and validation)
• Analyze timing reports and improve design quality
• Collaborate with RTL, DFT, and Physical Design teams
• Support timing closure during implementation and signoff
• Strong understanding of digital design fundamentals
• Knowledge of synthesis and STA flow
• Familiarity with timing concepts (setup, hold, skew, latency)
• Experience with EDA tools - Genus, Tempus
• Required relevant expertise for Malaysia is 5+ years and 10+ years of relevant expertise for other locations 
• Preferred immediate hires

             VISA SPONSORED FOR MALAYSIA

Employment Type  : Full time - Permanent

Work Location         : Bangalore, Cambridge, London, San Jose

Work Expertise        : 15+ years 

Desired Profile         :

• Expertise in Design for Test / DFT
• Expertise in coding using Verilog RTL, and scripting language like TCL, and/or Perl
• Proficient in Unix/Linux environments
• Expertise in Scan compression and insertion, Memory BIST, Logic BIST, JTAG/IJTAG, at-speed test, ATPG, fault simulation, back-annotated gate-level verification, silicon debug
• Expertise with Siemens, Cadence, and/or Synopsys DFT and simulation tools
• 15+ years of experience must include 10+ years of expertise in managing and leading DFT technical teams across different continents 
• Expertise in leading business strategy in the VLSI / Semiconductor Services / foundry business industry 
• Expertise in managing end to end projects including tape outs
• Must be willing to travel at short notice, relocate as per business needs 
• Must be willing to work onsite (customer premises) as per business needs
• Prior expertise in scaling large teams in services industry for the same technical domain is mandatory

Job Specs  : 

• Responsible for meeting delivery, revenue, operational, customer satisfaction targets and team management
• Hire and manage high caliber technical teams across GCC, ODC and onsite
• Develop, Drive high quality business / technology strategy and oversee the translation of this strategy into tactical action
• Uphold the organization's culture and long term missions
• Liaise and negotiate with various partners around the world to bring in new partnership.
• Synergize all company's resources and talents for the growth of company's business
• Oversee all sectors and fields of the business to ensure the company's competitiveness
• Provide leadership, direction, major decision making and resolution support to operations, projects and staff.
• Build strategic business partnerships and execute these opportunities through collaboration with external partners 

Employment Type  : Full time - Permanent

Work Location         : Bangalore, Cambridge, Edinburgh, London

Work Expertise        : 15+ years

Job Specs                 :             

• Expertise in Digital Verification 
• Expertise in Functional Verification 
• Expertise in SOC / IP Verification
• Expertise in working on system Verilog assertions & test benches
• Expertise in working on OVM / UVM / VMM based verification flow
• Expertise in working on ARM processor
• Expertise in working on AMBA bus protocols  (AXI, AHB, APB) 
• Expertise in CXL or PCIe or UCIe Protocol Verification
• Expertise in simulation tools (VCS, ModelSim, Questa)
• Expertise in driving Verification Strategy, writing Test Plan, developing Test Bench, Test cases.
• Expertise in analysing Code Coverage, Functional Coverage and Assertions.
• Expertise in verification of complex SoCs.
• Expertise in Test Plan creation and Verification technologies like Code Coverage, Functional coverage, assertion based verification.
• Expertise in Verification of complex datapath, DSP based ASICs 
• 15+ years of experience must include 10+ years of expertise in managing and leading ASIC DV technical teams across different continents 
• Expertise in leading business strategy in the VLSI / Semiconductor Services / foundry business industry 
• Expertise in managing end to end projects including tape outs
• Must be willing to travel at short notice, relocate as per business needs 
• Must be willing to work onsite (customer premises) as per business needs
• Prior expertise in scaling large teams in services industry for the same technical domain is mandatory

Job Specs  : 

• Responsible for meeting delivery, revenue, operational, customer satisfaction targets and team management
• Hire and manage high caliber technical teams across GCC, ODC and onsite
• Develop, Drive high quality business / technology strategy and oversee the translation of this strategy into tactical action
• Uphold the organization's culture and long term missions
• Liaise and negotiate with various partners around the world to bring in new partnership.
• Synergize all company's resources and talents for the growth of company's business
• Oversee all sectors and fields of the business to ensure the company's competitiveness
• Provide leadership, direction, major decision making and resolution support to operations, projects and staff.
• Build strategic business partnerships and execute these opportunities through collaboration with external partners

Employment Type    : Full time - Permanent

Work Location          : Bangalore, Mysore

Work Expertise         : 15+ years

Desired Profile  :       

• Bachelor's / Master's degree in engineering from EEE / E&C 
• Expertise in managing and leading technical teams across different continents 
• Expertise in leading business strategy in the VLSI / Semiconductor Services / foundry business industry 
• Expertise in managing end to end projects including tape outs
• Must be willing to travel at short notice, relocate as per business needs 
• Must be willing to work onsite (customer premises) as per business needs
• Expertise in working on any of the following technologies is mandatory :

1. ANALOG MIXED SIGNAL LAYOUT - finfet / high speed / planar technology nodes
2. ANALOG DESIGN - data converter / power management / pll
3. ANALOG VERIFICATION
4. ASIC PHYSICAL DESIGN
5. ASIC RTL DESIGN 
6. DFT DESIGN - jtag / mbist / lbist / scan
7. DIGITAL VERIFICATION - OVM / UVM / VMM
8. EDA CAD FLOW - tcl / primetime / design compiler

Job Specs         :       

• Responsible for meeting delivery, revenue, operational, customer satisfaction targets and team management
• Hire and manage high caliber technical teams across GCC, ODC and onsite
• Develop, Drive high quality business / technology strategy and oversee the translation of this strategy into tactical action
• Uphold the organization's culture and long term missions
• Liaise and negotiate with various partners around the world to bring in new partnership.
• Synergize all company's resources and talents for the growth of company's business
• Oversee all sectors and fields of the business to ensure the company's competitiveness
• Provide leadership, direction, major decision making and resolution support to operations, projects and staff.
• Build strategic business partnerships and execute these opportunities through collaboration with external partners 
• Resource must be a citizen of India residing across any states / Union Territories of India